Communication Series P1 : Uart, Spi And I2C In Verilog

Published 11/2023
MP4 | Video: h264, 1920×1080 | Audio: AAC, 44.1 KHz

A Step-by-Step Guide

What you’ll learn

Different Modes of SPI, Daisy Chain Configuration of SPI.

Bit Banging

Requirements

Fundamentals of Digital Electronics, Verilog.

Description

Overview

Lecture 4 Design Code

Lecture 5 TB Code

Lecture 11 FIFO TB

Lecture 12 Design Code

Lecture 13 Testbench Code

Lecture 19 Design Code

Lecture 20 TB Code

Lecture 23 Design Code

Lecture 24 TB Code

Lecture 31 Design Code

Lecture 32 TB Code

Lecture 33 Complete Design

Lecture 34 TX testbench

Lecture 35 Design Code

Lecture 36 TB Code

Section 2: SPI

Lecture 37 SPI protocol without different mode

Lecture 38 SPI Master P1

Lecture 39 SPI Master P2

Lecture 40 SPI Master P3

Lecture 41 Code

Lecture 42 SPI Slave P1

Lecture 43 SPI Slave P2

Lecture 44 Code

Lecture 45 Alternate Implementation

Lecture 46 Code

Lecture 47 Understanding CPOL behavior

Lecture 48 Implementation

Lecture 49 Code

Lecture 50 Understanding CPHA

Lecture 51 Understanding SPI Modes with different CPOL and CPHA

Lecture 52 Working with CPHA Master

Lecture 53 Master TB

Lecture 54 Code

Lecture 55 Working with CPHA Slave

Lecture 56 Code

Lecture 57 Digilent PMOD DA4 (Analog Devices AD5628) : Understanding Specifications

Lecture 58 Digilent PMOD DA4 (Analog Devices AD5628) : Master Design

Lecture 59 Digilent PMOD DA4 (Analog Devices AD5628) : TB

Lecture 60 Design Code

Lecture 61 TB Code

Lecture 62 Daisy Chain Configuration

Lecture 63 Master

Lecture 64 Slave

Lecture 65 Testbench

Lecture 66 Design Code

Lecture 67 TB Code

Lecture 68 One Notes

Section 3: I2C

Lecture 69 Overview

Lecture 70 Understanding I2C Open Drain Interface

Lecture 72 I2C Write and Read Transactions
Lecture 73 I2C Master FSM without Clock Stretch

Lecture 74 I2C Master without clock stretch

Lecture 75 Master TB

Lecture 76 Design Code

Lecture 77 TB Code

Lecture 78 I2C Slave without clock stretch

Lecture 79 Testbench for top

Lecture 80 Design Code

Lecture 81 TB Code

Lecture 82 Bit Banging

Lecture 83 Understanding Clock Stretching

Lecture 84 Implementation of Master

Lecture 85 Implementation of Slave

Lecture 86 Design Code

Lecture 87 TB Code

A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems.