Digital Ic/Fpga Design P4: Sta && Dc SynThesis

Digital Ic/Fpga Design P4: Sta && Dc Synthesis
Published 2/2025
MP4 | Video: h264, 1920×1080 | Audio: AAC, 44.1 KHz

Static Timing Analysis and DC Synthesis

What you’ll learn

Principle of STA

Basics of stander cell library

Characters of clock in STA

Setup/hold timing analysis for same clock

Common used timing constraints

Timing analysis for same clock domain (synchronous path)

Timing analysis for different clock domain (asynchronous path)

Synthesis example using Design Compiler (including whole TCL script)

Requirements

Basic knowledge of digital fundamental

Description

Overview

Section 1: Introduction

Lecture 1 Introduction of Static Timing Analysis

Section 2: Principle of STA

Lecture 2 Why need Static Timing Analysis

Lecture 3 Timing and DRC Check Types

Lecture 4 Cell Library and Delay Calculate

Section 3: Timing Analysis for Synchronous Path

Lecture 5 Charactors and Define of Clock in STA

Lecture 6 Terminology for STA

Lecture 7 Setup&&Hold Calculation for Timing Path of Same Clock

Senior undergraduate students of EE or higher,IC design/verification engineers with 0~2 year experience