Fundamentals Of Arm Architecture(Armv7A, Armv8A) Part 1

Published 9/2024
MP4 | Video: h264, 1920×1080 | Audio: AAC, 44.1 KHz

Practical course to teach Assembly instruction, Register and Exception level in Armv7-A and Armv8-A

What you’ll learn

Understand the basic working principles of Arm architecture (Armv8-A, Armv7-A)

Understand the registers in Arm architecture (Armv8-A, Armv7-A)

Learn the processor modes defined in Armv7-A

Understand the exception levels defined in Armv8-A

Use the hardware debugger program, TRACE32, effectively

Requirements

Computer Architecture

Microprocessor

Description

Overview

Section 1: Introduction

Section 2: Introducing Registers

Lecture 3 What is the register?

Lecture 4 How to learn about register?

Lecture 5 Armv7-A: Register Overview

Lecture 8 Armv7-A: banked register: R14_

Lecture 9 CPSR (The Current Program Status Register)

Lecture 10 SPSRs (The Special Program Status Register)

Lecture 11 How SPSRs are updated (Interrupt)

Section 5: Armv8-A – Register

Lecture 12 Introducing register in Armv8-A

Lecture 13 General-purpose registers

Lecture 14 Special Registers

Lecture 15 ELR_ELx – Exception link register

Lecture 16 Introducing SPSR_ELx register

Lecture 17 How is SPSR_ELx register updated during generation of exception

Section 6: Mastering Register with TRACE32 debugging

Lecture 18 Armv7-A: Identify the general-purpose register

Section 7: Armv8-A: System registers

Lecture 21 Introducing System registers in Armv8-A

Lecture 22 Example of system register – HCR_EL2

Lecture 23 The lowest exception level for system registers

Lecture 24 Write or Read the system registers: MSR and MRS

Section 8: Introducing Assembly instruction

Lecture 25 What is it challenging to learn about assembly instruction?

Lecture 26 What can we do using assembly instruction: 1. Bringup

Lecture 27 What can we do using assembly instruction: 2. Develop device driver

Lecture 28 What can we do using assembly instruction: 3. Improve debugging ability

Lecture 29 Basic form of assembly instruction

Lecture 30 MOVE instruction

Section 9: Arithmetic instruction

Lecture 31 ADD instruction

Lecture 32 ADD instruction (TRACE32 practice)

Lecture 33 SUB instruction

Lecture 34 SUB instruction (TRACE32 practice)

Section 10: Logical operation

Lecture 35 AND instruction

Lecture 36 AND instruction (TRACE32 debugging)

Lecture 37 ORR instruction

Lecture 38 ORR instruction (TRACE32 debugging)

Lecture 39 ORN instruction

Lecture 40 BIC instruction

Lecture 41 EOR instruction

Section 11: Bit shift operation

Lecture 42 Introducing Bit Shift operation

Lecture 43 LSL instruction

Lecture 44 LSR instruction

Section 12: Branch operation

Lecture 45 B instruction

Lecture 46 BL instruction

Lecture 47 BX instruction – Armv7

Lecture 48 BLX instruction – Armv7

Lecture 49 BX, BLX instruction (TRACE32 Debugging Practice)

Lecture 50 BR instruction – Armv8

Lecture 51 BLR instruction – Armv8

Section 13: Conditional branch operation

Lecture 54 Introduction to conditional operation

Lecture 55 CBZ instruction

Lecture 56 CBNZ instruction

Lecture 57 TBZ instruction

Lecture 58 TBZ instruction (TRACE32 debugging)

Lecture 59 TBNZ instruction

Lecture 60 TBNZ instruction (TRACE32 debugging)

Section 14: Exception-generating instruction

Lecture 61 SVC instruction

Lecture 62 HVC instruction

Lecture 63 SMC instruction

Section 15: Memory Access operation

Section 16: Processor mode(Armv7-A)

Lecture 68 User mode

Lecture 69 Supervisor mode

Lecture 70 IRQ mode and FIQ mode

Lecture 71 Abort mode

Lecture 72 Undefined mode

Lecture 73 Introduction to Exception level in Armv8 architecture

Lecture 74 Exception level-Arm specification review

Lecture 75 Why BSP software engineer should learn Exception Levels?

Lecture 76 Details of EL0(User application) in Linux system

Lecture 77 Example code at EL0 in Linux system

Lecture 78 EL0 in Virtualization and TrustZone feature

Lecture 79 Exception level change at EL0 in virtualization (Big picture)

Lecture 80 Details of EL1(Linux kernel) in Linux system

Lecture 81 Highlight: Exception handling at EL1

Lecture 82 Memory abort Exception handling at EL1

Lecture 83 Memory system in case of Memory abort

Lecture 84 IRQ(Interrupt) Exception handling at EL1

Lecture 85 IRQ(Interrupt) handling – Software point of view

Lecture 86 Read CurrentEL system register to identify exception level

Lecture 87 Enter EL1 from EL0 via SVC instruction

Lecture 88 Enter EL2 from EL1 via HVC instruction

System software engineer (Linux BSP engineer),Chipset BSP and firmware software engineer,Automotive system software engineer,System software engineers who are eager to level up debugging skills,Professionals interested in exploring Armv8 and Armv7 architecture