Fundamentals of Verification and System Verilog

Fundamentals of Verification and System Verilog
Last updated 7/2020
Duration: 21h 42m | .MP4 1920×1080, 30 fps(r) | AAC, 44100 Hz, 2ch | 8.14 GB

Simple course for students and engineers who wants to learn concepts of verification and basic SystemVerilog Constructs

What you’ll learn
– Significance of verification
– Verification options, methodologies, approaches and plan
– Examples to practice on verification tool EDA Playground
– Testbench Fundamentals
– Writing your SystemVerilog code
– Procedural Statements
– Interface Concepts

Requirements
– Verilog programming and fundamentals of FPGA programming are supposed to be already known
– Familiarity with C and C++ will be an added advantage
– Knowledge of digital circuit design

Description
Who this course is for:
– This course is for students and engineers who wants to learn basics of verification and basic constructs of SystemVerilog
– Verification engineers who wants to refresh concepts of SystemVerilog
– Job seekers in verification industry
More Info

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